Xilinx virtex-5 fpga

40 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 1: Clock Resources
Regional Clocking Resources
Regional clock networks are a set of clock networks independent of the global clock
network. Unlike global clocks, the span of a regional clock signal (BUFR) is limited to three
clock regions, while the I/O clock signal drives a single region only. These networks are
especially useful for source-synchronous interface designs. The I/O banks in Virtex-5
devices are the same size as a clock region.
To understand how regional clocking works, it is important to understand the signal path
of a regional clock signal. The regional clocking resources and network in Virtex-5 devices
consist of the following paths and components:
• Clock Capable I/O
• I/O Clock Buffer - BUFIO
• Regional Clock Buffer - BUFR
• Regional Clock Nets
Clock Capable I/O
In a typical clock region there are four clock-capable I/O pin pairs (there are exceptions in
the center column). Clock-capable I/O pairs are regular I/O pairs in select locations with
special hardware connections to nearby regional clock resources. Some global clock inputs
are also clock-capable I/Os. There are four dedicated clock-capable I/O sites in every
bank. When used as clock inputs, clock-capable pins can drive BUFIO and BUFR. Clock-
capable I/Os in the center column can not drive BUFRs. Clock-capable I/Os can not
directly connect to the global clock buffers. When used as single-ended clock pins, then as
described in “Global Clock Buffers,” the P-side of the pin pair must be used because a
direct connection only exists on this pin.