Xilinx virtex-5 fpga User Manual

152 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 4: Block RAM
Clock Event 2 and Clock Event 4: Write Operation and Deassertion of Almost
EMPTY Signal
Three read-clock cycles after the fourth data is written into the FIFO, the Almost EMPTY
pin is deasserted to signify that the FIFO is not in the almost EMPTY state.
For the example in Figure 4-21, the timing diagram is drawn to reflect FWFT mode. Clock
event 2 is with respect to write-clock, while clock event 4 is with respect to read-clock.
Clock event 4 appears three read-clock cycles after clock event 2.
• At time T
FDCK_DI
, before clock event 2 (WRCLK), data 03 becomes valid at the DI
inputs of the FIFO.
• Write enable remains asserted at the WREN input of the FIFO.
• At clock event 4, DO output pins of the FIFO remains at 00 since no read has been
performed. In the case of standard mode, data 00 will never appear at the DO output
pins of the FIFO.
• At time T
FCKO_AEMPTY
, after clock event 4 (RDCLK), almost empty is deasserted at
the AEMPTY pin. In the case of standard mode, AEMPTY deasserts in the same way
as in FWFT mode.
If the rising WRCLK edge is close to the rising RDCLK edge, AEMPTY could be deasserted
one RDCLK period later.
Case 2: Writing to a Full or Almost Full FIFO
Prior to the operations performed in Figure 4-22, the FIFO is almost completely full. In this
example, the timing diagram reflects of both standard and FWFT modes.
X-Ref Target - Figure 4-22
Figure 4-22: Writing to a Full / Almost Full FIFO
ug190_4_18_012605
00 01 02 03 04 05 06
WRCLK
WREN
DI
RDCLK
RDEN
FULL
AFULL
WRERR
1 42
3
T
FDCK_DI
T
FDCK_DI
T
FDCK_DI
T
FCKO_AFULL
T
FCKO_WERR
T
FCKO_FULL
T
FCCK_WREN
T
FCKO_WERR
T
FCCK_WREN

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English