Xilinx virtex-5 fpga - HSTL Class III

Virtex-5 FPGA User Guide www.xilinx.com 259
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
HSTL Class III
Figure 6-49 shows a sample circuit illustrating a valid termination technique for HSTL
Class III.
Table 6-19 lists the HSTL Class III DC voltage specifications.
X-Ref Target - Figure 6-49
Figure 6-49: HSTL Class III Termination
Table 6-19: HSTL Class III DC Voltage Specifications
Min Typ Max
V
CCO
1.40 1.50 1.60
V
REF
(2)
–0.90–
V
TT
–V
CCO
–
V
IH
V
REF
+0.1 – –
V
IL
––V
REF
–0.1
V
OH
V
CCO
–0.4 – –
V
OL
– – 0.4
I
OH
at V
OH
(mA)
(1)
–8 – –
I
OL
at V
OL
(mA)
(1)
24 – –
Notes:
1. V
OL
and V
OH
for lower drive currents are sample tested.
2. Per EIA/JESD8-6, “The value of V
REF
is to be selected by the user to provide optimum noise margin in
the use conditions specified by the user.”
Z
0
IOB
IOB
HSTL_III
HSTL_III
ug190_6_47_030306
V
TT
= 1.5V
R
P
= Z
0
= 50Ω
Z
0
IOB
IOB
HSTL_III_DCI HSTL_III_DCI
V
CCO
= 1.5V
R
VRP
= Z
0
= 50Ω
V
REF
= 0.9V
+
–
V
REF
= 0.9V
+
–
External Termination
DCI