Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 83
UG190 (v5.0) June 19, 2009
VHDL and Verilog Templates, and the Clocking Wizard
VHDL and Verilog Templates, and the Clocking Wizard
VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives. In addition, VHDL and Verilog files are generated by the Clocking Wizard in
the ISE software. The Clocking Wizard sets appropriate DCM attributes, input/output
clocks, and buffers for general use cases.
X-Ref Target - Figure 2-16
Figure 2-16: Two DCMs Driving a PLL
IBUFG
BUFG
BUFG
ug190_2_18_040906
BUFG
BUFG
BUFG
CLKIN CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX180
CLKFX
CLKFBIN
DCM
CLKIN CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX180
CLKFX
CLKFBIN
DCM1
RST
CLKIN1
CLKIN2
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLKFBOUT
RST
CLKFBIN
PLL
IBUFG

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English