Xilinx virtex-5 fpga - ECC Decode-Only

Virtex-5 FPGA User Guide www.xilinx.com 167
UG190 (v5.0) June 19, 2009
Built-in Error Correction
Similarly, at time T2W and T3W, DI[63:0] = B and C, together with their corresponding
parity bits PB (hex) and PC (hex) are written into memory locations b and c. PB and PC
appear at output ECCPARITY[7:0] shortly after T2W and T3W.
ECC Encode-Only Read
ECC encode-only read is identical to normal block RAM read. 64-bit data appears at
DO[63:0] and 8-bit parity appears at DOP[7:0]. Single-bit error correction does not happen,
and the error flags SBITERR and DBITERR is never asserted.
ECC Decode-Only
Set by Attributes
EN_ECC_READ = TRUE
EN_ECC_WRITE = FALSE
In ECC decode-only, only the ECC decoder is enabled. The ECC encoder is disabled.
Decode-only mode is used to inject single-bit or double-bit errors to test the functionality
of the ECC decoder. The ECC parity bits must be externally supplied using the DIP[7:0]
pins.
Using ECC Decode-Only to Inject Single-Bit Error
• At time T1W, T2W, T3W, DI[63:0] = A, B, C with single-bit error and DIP[7:0] = PA
(hex), PB (hex), PC (hex), the corresponding ECC parity bits for A, B, and C are
written into memory locations a, b, and c.
• At time T1R, T2R, T3R, the contents of address a, b, and c are read out and corrected as
needed.
• Latch mode: DO[63:0] = A, B, C, DOP[7:0] = PA, PB, PC shortly after T1R, T2R, T3R.
• Register mode: DO[63:0] = A, B, C, DOP[7:0] = PA, PB, PC shortly after T2R, T3R, T4R.
• SBITERR lines up with the corresponding DO/DOP data.
The ECC decoder also corrects single-bit error in parity bits.
Using the ECC Decode-Only to Inject Double-Bit Error
• At time T1W, T2W, T3W, DI[63:0] = A, B, C with double-bit error and DIP[7:0] = PA
(hex), PB (hex), PB (hex), the corresponding ECC parity bits for A, B, and C are written
into memory location a, b, and c.
• At time T1R, T2R, T3R, the original contents of address a, b, and c are read out and a
double-bit error is detected.
• Latch mode: DO[63:0] = A, B, C with double-bit error, DOP[7:0] = PA, PB, PC shortly
after T1R, T2R, T3R.
• Register mode: DO[63:0] = A, B, C with double-bit error, DOP[7:0] = PA, PB, PC
shortly after T2R, T3R, T4R.
• DBITERR lines up with the corresponding DO/DOP data.
The ECC decoder also detects when double-bit error in parity bits occurs, and when a
single-bit error in the data bits and a single-bit error in the corresponding parity bits
occurs.