Xilinx virtex-5 fpga

230 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
♦ DCI outputs that do not require reference resistors on VRP/VRN:
HSTL_I_DCI
HSTL_III_DCI
HSTL_I_DCI_18
HSTL_III_DCI_18
SSTL2_I_DCI
SSTL18_I_DCI
♦ DCI inputs that do not require reference resistors on VRP/VRN:
LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
4. The value of the external reference resistors should be selected to give the desired
output impedance. If using GTL_DCI, HSTL_DCI, or SSTL_DCI I/O standards, then
the external reference resistors should be 50 Ω.
5. The values of the reference resistors must be within the supported range
(20 Ω– 100 Ω).
6. Follow the DCI I/O banking rules:
a. V
REF
must be compatible for all of the inputs in the same bank.
b. V
CCO
must be compatible for all of the inputs and outputs in the same bank.
c. No more than one DCI I/O standard using single termination type is allowed per
bank.
d. No more than one DCI I/O standard using split termination type is allowed per
bank.
e. Single termination and split termination, controlled impedance driver, and
controlled impedance driver with half impedance can co-exist in the same bank.
7. Master DCI is not supported in Banks 1 and 2.
The behavior of a DCI 3-state outputs is as follows:
If a LVDCI or LVDCI_DV2 driver is in 3-state, the driver is 3-stated. If a driver with single
or split termination is in 3-state, the driver is 3-stated but the termination resistor remains.
The following section lists actions that must be taken for each DCI I/O standard.
DCI Usage Examples
• Figure 6-16 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI,
HSTL_III_DCI, and HSTL_IV_DCI I/O standards.
• Figure 6-17 provides examples illustrating the use of the SSTL2_I_DCI and
SSTL2_II_DCI I/O standards.