Xilinx virtex-5 fpga User Manual

288 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
SSTL18 Class II (1.8V)
Figure 6-80 shows a sample circuit illustrating a valid unidirectional termination technique
for SSTL Class II (1.8V).
Figure 6-81 shows a sample circuit illustrating a valid bidirectional termination technique
for SSTL (1.8V) Class II.
X-Ref Target - Figure 6-80
Figure 6-80: SSTL18 (1.8V) Class II Unidirectional Termination
Z
0
IOB
IOB
SSTL18_IISSTL18_II
ug190_6_75_030506
V
TT
= 0.9V
R
P
= Z
0
= 50Ω
V
TT
= 0.9V
R
P
= Z
0
= 50Ω
Z
0
IOB
IOB
SSTL18_II_DCI
SSTL18_II_DCI
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
REF
= 0.9V
+
–
V
REF
= 0.9V
+
–
External Termination
DCI
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
R
S
= 20Ω
R
0
= 20Ω

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English