Xilinx virtex-5 fpga - 1 X Output Clock, 90° Phase Shift - CLK90; 1 X Output Clock, 180° Phase Shift - CLK180; 1 X Output Clock, 270° Phase Shift - CLK270; 2 X Output Clock - CLK2 X

Virtex-5 FPGA User Guide www.xilinx.com 55
UG190 (v5.0) June 19, 2009
DCM Ports
1x Output Clock, 90° Phase Shift - CLK90
The CLK90 output clock provides a clock with the same frequency as the DCM’s CLK0
phase-shifted by 90°.
1x Output Clock, 180° Phase Shift - CLK180
The CLK180 output clock provides a clock with the same frequency as the DCM’s CLK0
phase-shifted by 180°.
1x Output Clock, 270° Phase Shift - CLK270
The CLK270 output clock provides a clock with the same frequency as the DCM’s CLK0
phase-shifted by 270°.
2x Output Clock - CLK2X
The CLK2X output clock provides a clock that is phase aligned to CLK0, with twice the
CLK0 frequency, and with an automatic 50/50 duty-cycle correction. Until the DCM is
locked, the CLK2X output appears as a 1x version of the input clock with a 25/75 duty
cycle. This behavior allows the DCM to lock on the correct edge with respect to the source
clock.
2x Output Clock, 180° Phase Shift - CLK2X180
The CLK2X180 output clock provides a clock with the same frequency as the DCM’s
CLK2X phase-shifted by 180°.
Frequency Divide Output Clock - CLKDV
The CLKDV output clock provides a clock that is phase aligned to CLK0 with a frequency
that is a fraction of the effective CLKIN frequency. The fraction is determined by the
CLKDV_DIVIDE attribute. Refer to the CLKDV_DIVIDE Attribute for more information.
Frequency-Synthesis Output Clock - CLKFX
The CLKFX output clock provides a clock with the following frequency definition:
CLKFX frequency = (M/D) × effective CLKIN frequency
In this equation, M is the multiplier (numerator) with a value defined by the
CLKFX_MULTIPLY attribute. D is the divisor (denominator) with a value defined by the
CLKFX_DIVIDE attribute. Specifications for M and D, as well as input and output
frequency ranges for the frequency synthesizer, are provided in the Virtex-5 FPGA Data
Sheet.
The rising edge of CLKFX output is phase aligned to the rising edges of CLK0, CLK2X, and
CLKDV. When M and D to have no common factor, the alignment occurs only once every
D cycles of CLK0.
Frequency-Synthesis Output Clock, 180° - CLKFX180
The CLKFX180 output clock provides a clock with the same frequency as the DCM’s
CLKFX phase-shifted by 180°.