Xilinx virtex-5 fpga User Manual

50 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 2: Clock Management Technology
DCM Primitives
The DCM primitives DCM_BASE and DCM_ADV are shown in Figure 2-2.
DCM_BASE Primitive
The DCM_BASE primitive accesses the basic frequently used DCM features and simplifies
the user-interface ports. The clock deskew, frequency synthesis, and fixed-phase shifting
features are available to use with DCM_BASE. Table 2-2 lists the available ports in the
DCM_BASE primitive.
X-Ref Target - Figure 2-2
Figure 2-2: DCM Primitives
CLKIN
CLKFB
RST
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
CLKIN
CLKFB
PSINCDEC
PSEN
PSCLK
DADDR[6:0]
DI[15:0]
DWE
DEN
DCLK
RST
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
PSDONE
DO[15:0]
DRDY
DCM_ADVDCM_BASE
ug190_2_02_042706
Table 2-2: DCM_BASE Primitive
Available Ports Port Names
Clock Input CLKIN, CLKFB
Control and Data Input RST
Clock Output CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
Status and Data Output LOCKED

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English