Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 279
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
SSTL2 Class II (2.5V)
Figure 6-70 shows a sample circuit illustrating a valid unidirectional termination technique
for SSTL2 Class II.
X-Ref Target - Figure 6-70
Figure 6-70: SSTL2 Class II with Unidirectional Termination
Z
0
IOB
IOB
SSTL2_II
SSTL2_II
ug190_6_66_030506
V
TT
= 1.25V
R
P
= Z
0
= 50Ω
V
TT
= 1.25V
R
P
= Z
0
= 50Ω
Z
0
IOB
IOB
SSTL2_II_DCI
SSTL2_II_DCI
V
CCO
= 2.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
REF
= 1.25V
+
–
V
REF
= 1.25V
+
–
External Termination
DCI
V
CCO
= 2.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
R
0
= 25Ω
25Ω

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English