Xilinx virtex-5 fpga User Manual

280 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
Figure 6-71 shows a sample circuit illustrating a valid bidirectional termination technique
for SSTL2 Class II.
X-Ref Target - Figure 6-71
Figure 6-71: SSTL2 Class II with Bidirectional Termination
Z
0
IOB
SSTL2_II
ug190_6_67_030506
V
TT
= 1.25V
R
P
= Z
0
= 50Ω
V
TT
= 1.25V
R
P
= Z
0
= 50Ω
Z
0
IOB
IOB
SSTL2_II_DCI
SSTL2_II_DCI
V
CCO
= 2.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
REF
= 1.25V
+
–
V
REF
= 1.25V
+
–
External Termination
DCI
V
CCO
= 2.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
IOB
SSTL2_II
R
S
= 25Ω R
S
= 25Ω
R
0
= 25Ω
V
REF
= 1.25V
V
REF
= 1.25V
R
0
= 25Ω

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English