Xilinx virtex-5 fpga User Manual

200 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 5: Configurable Logic Blocks (CLBs)
to create an adder/accumulator. CYINIT is the CIN of the first bit in a carry chain. The
CYINIT value can be 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry
bit). The CIN input is used to cascade slices to form a longer carry chain. The O outputs
contain the sum of the addition/subtraction. The CO outputs compute the carry out for
each bit. CO3 is connected to COUT output of a slice to form a longer carry chain by
cascading multiple slices. The propagation delay for an adder increases linearly with the
number of bits in the operand, as more carry chains are cascaded. The carry chain can be
implemented with a storage element or a flip-flop in the same slice.
CLB / Slice Timing Models
Due to the large size and complexity of Virtex-5 FPGAs, understanding the timing
associated with the various paths and functional elements is a difficult and important task.
Although it is not necessary to understand the various timing parameters to implement
most designs using Xilinx software, a thorough timing model can assist advanced users in
analyzing critical paths or planning speed-sensitive designs.
Three timing model sections are described:
• Functional element diagram – basic architectural schematic illustrating pins and
connections
• Timing parameters – definitions of Virtex-5 FPGA Data Sheet timing parameters
• Timing Diagram - illustrates functional element timing parameters relative to each
other
Use the models in this chapter in conjunction with both the Xilinx Timing Analyzer
software (TRCE) and the section on switching characteristics in the Virtex-5 FPGA Data
Sheet. All pin names, parameter names, and paths are consistent with the post-route timing
and pre-route static timing reports. Most of the timing parameters found in the section on
switching characteristics are described in this chapter.
All timing parameters reported in the Virtex-5 FPGA Data Sheet are associated with slices
and CLBs. The following sections correspond to specific switching characteristics sections
in the Virtex-5 FPGA Data Sheet:
• “General Slice Timing Model and Parameters” (CLB Switching Characteristics)
• “Slice Distributed RAM Timing Model and Parameters (Available in SLICEM only)”
(CLB Distributed RAM Switching Characteristics)
• “Slice SRL Timing Model and Parameters (Available in SLICEM only)” (CLB SRL
Switching Characteristics)
• “Slice Carry-Chain Timing Model and Parameters” (CLB Application Switching
Characteristics)

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English