Xilinx virtex-5 fpga

256 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
Table 6-17 lists the HSTL (1.5V) Class II DC voltage specifications.
Differential HSTL Class II
Figure 6-45 shows a sample circuit illustrating a valid termination technique for
differential HSTL Class II (1.5V) with unidirectional termination.
Table 6-17: HSTL (1.5V) Class II DC Voltage Specifications
Min Typ Max
V
CCO
1.40 1.50 1.60
V
REF
(2)
0.68 0.75 0.90
V
TT
– V
CCO
× 0.5 –
V
IH
V
REF
+0.1 – –
V
IL
––V
REF
–0.1
V
OH
V
CCO
–0.4 – –
V
OL
– – 0.4
I
OH
at V
OH
(mA)
(1)
–16 – –
I
OL
at V
OL
(mA)
(1) (3)
16 – –
Notes:
1. V
OL
and V
OH
for lower drive currents are sample tested.
2. Per EIA/JESD8-6, “The value of V
REF
is to be selected by the user to provide optimum noise margin in
the use conditions specified by the user.”
3. HSTL_II_T_DCI has a weaker driver than HSTL_II_DCI.
X-Ref Target - Figure 6-45
Figure 6-45: Differential HSTL (1.5V) Class II Unidirectional Termination
ug190_6_40_030206
+
–
External Termination
Z
0
IOB
IOB
DIFF_HSTL_II
DIFF_HSTL_II
Z
0
DIFF_HSTL_II
V
TT
= 0.75V
50Ω
V
TT
= 0.75V
50Ω
V
TT
= 0.75V
50Ω
V
TT
= 0.75V
50Ω