Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 255
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
Figure 6-44 shows a sample circuit illustrating a valid termination technique for HSTL
Class II (1.5V) with bidirectional termination.
X-Ref Target - Figure 6-44
Figure 6-44: HSTL (1.5V) Class II Bidirectional Termination
Z
0
IOB
IOB
HSTL_II
HSTL_II
ug190_6_42_030306
V
TT
= 0.75V
R
P
= Z
0
= 50Ω
V
TT
= 0.75V
R
P
= Z
0
= 50Ω
Z
0
IOB
IOB
HSTL_II_DCI
HSTL_II_DCI
V
CCO
= 1.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
REF
= 0.75V
V
REF
= 0.75V
+
–
V
REF
= 0.75V
+
–
External Termination
DCI
V
CCO
= 1.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
REF
= 0.75V

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English