Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 237
UG190 (v5.0) June 19, 2009
Virtex-5 FPGA SelectIO Primitives
Output Slew Rate Attributes
A variety of attribute values provide the option of choosing the desired slew rate for
single-ended I/O output buffers. For LVTTL and LVCMOS output buffers (OBUF, OBUFT,
and IOBUF), the desired slew rate can be specified with the SLEW attribute.
The allowed values for the SLEW attribute are:
• SLEW = SLOW (Default)
• SLEW = FAST
The SLEW attribute uses the following syntax in the UCF file:
INST <I/O_BUFFER_INSTANTIATION_NAME> SLEW = "<SLEW_VALUE>";
By the default, the slew rate for each output buffer is set to SLOW. This is the default used
to minimize the power bus transients when switching non-critical signals.
Output Drive Strength Attributes
For LVTTL and LVCMOS output buffers (OBUF, OBUFT, and IOBUF), the desired drive
strength (in mA) can be specified with the DRIVE attribute.
The allowed values for the DRIVE attribute are:
• DRIVE = 2
• DRIVE = 4
• DRIVE = 6
• DRIVE = 8
• DRIVE = 12 (Default)
• DRIVE = 16
• DRIVE = 24
LVCMOS12 only supports the 2, 4, 6, 8 mA DRIVE settings. LVCMOS15 and LVCMOS18
only support the 2, 4, 6, 8, 12, and 16 mA DRIVE settings.
The DRIVE attribute uses the following syntax in the UCF file:
INST <I/O_BUFFER_INSTANTIATION_NAME> DRIVE = "<DRIVE_VALUE>";
PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF
When using 3-state output (OBUFT) or bidirectional (IOBUF) buffers, the output can have
a weak pull-up resistor, a weak pull-down resistor, or a weak “keeper” circuit. For input
(IBUF) buffers, the input can have either a weak pull-up resistor or a weak pull-down
resistor. This feature can be invoked by adding the following possible constraint values to
the relevant net of the buffers:
• PULLUP
• PULLDOWN
• KEEPER
Differential Termination Attribute
The differential termination (DIFF_TERM) attribute is designed for the Virtex-5 FPGA
supported differential input I/O standards. It is used to turn the built-in, 100Ω, differential
termination on or off.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English