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Xilinx virtex-5 fpga User Manual

Xilinx virtex-5 fpga
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Virtex-5 FPGA User Guide www.xilinx.com 317
UG190 (v5.0) June 19, 2009
Chapter 7
SelectIO Logic Resources
Introduction
This chapter describes the logic directly behind the I/O drivers and receivers covered in
Chapter 6, “SelectIO Resources.”
Virtex-5 FPGAs contain all of the basic I/O logic resources from Virtex-II/Virtex-II Pro
FPGAs. These resources include the following:
Combinatorial input/output
3-state output control
Registered input/output
Registered 3-state output control
Double-Data-Rate (DDR) input/output
DDR output 3-state control
In addition, Virtex-5 FPGAs implement the following architectural features that are also
supported in Virtex-4 FPGAs:
IODELAY provides users control of an adjustable, fine-resolution delay element
SAME_EDGE output DDR mode
SAME_EDGE and SAME_EDGE_PIPELINED input DDR mode

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Xilinx virtex-5 fpga Specifications

General IconGeneral
BrandXilinx
Modelvirtex-5 fpga
CategoryComputer Hardware
LanguageEnglish

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