Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 195
UG190 (v5.0) June 19, 2009
CLB Overview
delay to access the LUT. This operation is asynchronous and independent of the clock and
clock-enable signals.
Static Read Operation
If the 5-bit address is fixed, the Q output always uses the same bit position. This mode
implements any shift-register length from 1 to 16 bits in one LUT. The shift register length
is (N+1), where N is the input address (0 – 31).
The Q output changes synchronously with each shift operation. The previous bit is shifted
to the next position and appears on the Q output.
Shift Register Summary
• A shift operation requires one clock edge.
• Dynamic-length read operations are asynchronous (Q output).
• Static-length read operations are synchronous (Q output).
• The data input has a setup-to-clock timing specification.
• In a cascadable configuration, the Q31 output always contains the last bit value.
• The Q31 output changes synchronously after each shift operation.
Multiplexers
Function generators and associated multiplexers in Virtex-5 FPGAs can implement the
following:
• 4:1 multiplexers using one LUT
• 8:1 multiplexers using two LUTs
• 16:1 multiplexers using four LUTs
These wide input multiplexers are implemented in one level or logic (or LUT) using the
dedicated F7AMUX, F7BMUX, and F8MUX multiplexers. These multiplexers allow LUT
combinations of up to four LUTs in a slice.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English