Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 27
UG190 (v5.0) June 19, 2009
Global Clocking Resources
Global Clock Buffers
There are 32 global clock buffers in every Virtex-5 device. Each half of the die (top/bottom)
contains 16 global clock buffers. A global clock input can directly connect from the P-side
of the differential input pin pair to any global clock buffer input in the same half, either top
or bottom, of the device. Each differential global clock pin pair can connect to either a
differential or single-ended clock on the PCB. If using a single-ended clock, then the P-side
of the pin pair must be used because a direct connection only exists on this pin. For pin
naming conventions please refer to the Virtex-5 Family Packaging Specifications. A single-
ended clock must be connected to the positive (P) side of the differential global clock pins.
If a single-ended clock is connected to the P-side of a differential pin pair, then the N-side
can not be used as another single-ended clock pin. However, it can be used as a user I/O.
The 20 global clock pins on Virtex-5 devices can be connected to 20 differential or 20 single-
ended board clocks.
Global clock buffers allow various clock/signal sources to access the global clock trees and
nets. The possible sources for input to the global clock buffers include:
• Global clock inputs
• Clock Management Tile (CMT) outputs including:
♦ Digital Clock Managers (DCMs)
♦ Phase-Locked Loops (PLLs)
• Other global clock buffer outputs
• General interconnect
The global clock buffers can only be driven by sources in the same half of the die
(top/bottom).
All global clock buffers can drive all clock regions in Virtex-5 devices. The
primary/secondary rules from Virtex-II and Virtex-II Pro FPGAs do not apply. However,
only ten different clocks can be driven in a single clock region. A clock region (20 CLBs) is
a branch of the clock tree consisting of ten CLB rows up and ten CLB rows down. A clock
region only spans halfway across the device.
The clock buffers are designed to be configured as a synchronous or asynchronous glitch-
free 2:1 multiplexer with two clock inputs. Virtex-5 FPGA control pins provide a wide
range of functionality and robust input switching. The following subsections detail the
various configurations, primitives, and use models of the Virtex-5 FPGA clock buffers.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English