Xilinx virtex-5 fpga

276 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
SSTL2 Class I (2.5V)
Figure 6-67 shows a sample circuit illustrating a valid termination technique for SSTL2
Class I.
X-Ref Target - Figure 6-67
Figure 6-67: SSTL2 Class I Termination
Z
0
IOB
SSTL2_I
R
S
= 25Ω
IOB
SSTL2_I_DCI
R
0
= 25Ω
Z
0
IOB
SSTL2_I
ug190_6_63_030506
V
TT
= 1.25V
R
P
= Z
0
= 50Ω
Z
0
IOB
SSTL2_I_DCI
V
CCO
= 2.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
REF
= 1.25V
+
–
V
REF
= 1.25V
+
–
External Termination
DCI