Xilinx virtex-5 fpga - 3-State Parallel-To-Serial Conversion; OSERDES Primitive

Virtex-5 FPGA User Guide www.xilinx.com 371
UG190 (v5.0) June 19, 2009
Output Parallel-to-Serial Logic Resources (OSERDES)
3-State Parallel-to-Serial Conversion
In addition to parallel-to-serial conversion of data, an OSERDES module also contains a
parallel-to-serial converter for 3-state control of the IOB. Unlike data conversion, the
3-state converter can only serialize up to four bits of parallel 3-state signals. The 3-state
converter cannot be cascaded.
OSERDES Primitive
The OSERDES primitive is shown in Figure 8-15.
Table 8-5: CLK/CLKDIV Relationship of the Data Parallel-to-Serial Converter
Input Data Width Output in SDR
Mode
Input Data Width Output in DDR
Mode
CLK CLKDIV
2 4 2X X
3 6 3X X
4 8 4X X
5105XX
6 – 6X X
7 – 7X X
8 – 8X X
X-Ref Target - Figure 8-15
Figure 8-15: OSERDES Primitive
ug190_8_15_100307
CLK
CLKDIV
D1
D2
D3
D4
D5
D6
OCE
SHIFTIN1
SHIFTIN2
SR
T1
T2
T3
T4
TCE
OQ
SHIFTOUT1
SHIFTOUT2
TQ
OSERDES
Primitive