Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 379
UG190 (v5.0) June 19, 2009
Output Parallel-to-Serial Logic Resources (OSERDES)
Timing Characteristics of 8:1 DDR Serialization
Figure 8-18 illustrates the timing of an 8:1 DDR data serialization. In contrast to the 2:1 SDR
example, a second OSERDES is required to achieve an 8:1 serialization. The two OSERDES
are connected and configured using the methods described in “OSERDES Width
Expansion,” page 375. Six of the eight bits are connected to D1–D6 of the master OSERDES
while the remaining two bits are connected to D3–D4 of the slave OSERDES.
Clock Event 1
On the rising edge of CLKDIV, the word ABCDEFGH is driven from the FPGA logic to the
D1–D6 inputs of the master OSERDES and D3–D4 of the slave OSERDES (after some
propagation delay).
Clock Event 2
On the rising edge of CLKDIV, the word ABCDEFGH is sampled into the master and slave
OSERDES from the D1–D6 and D3–D4 inputs, respectively.
Clock Event 3
The data bit A appears at OQ four CLK cycles after ABCDEFGH is sampled into the
OSERDES. This latency is consistent with the Table 8-10 listing of a 8:1 DDR mode
OSERDES latency of four CLK cycles.
X-Ref Target - Figure 8-18
Figure 8-18: OSERDES Data Flow and Latency in 8:1 DDR Mode
Clock
Event 1
UG190_8_18_100307
Master.D1
Master.D2
Master.D3
Master.D4
Master.D5
Master.D6
Slave.D3
Slave.D4
AI
BJ
CK
DL
EM
FN
GO
HP
CLKDIV
CLK
ABCDEFGHI
OQ
Clock
Event 2
Clock
Event 3
Clock
Event 4

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English