Xilinx virtex-5 fpga - Slice SRL Timing Model and Parameters (Available in SLICEM Only)

Virtex-5 FPGA User Guide www.xilinx.com 207
UG190 (v5.0) June 19, 2009
CLB / Slice Timing Models
Slice SRL Timing Model and Parameters (Available in SLICEM only)
Figure 5-29 illustrates shift register implementation in a Virtex-5 FPGA slice. Some
elements of the slice have been omitted for clarity. Only the elements relevant to the timing
paths described in this section are shown.
X-Ref Target - Figure 5-29
Figure 5-29: Simplified Virtex-5 FPGA Slice SRL
UG190_5_29_050506
6
D
DX
CX
BX
AX
D address
SRL
CLK WE
DI1
A
O6
MC31
W
CLK
6
C
C address
SRL
CLK WE
DI1
A
O6
MC31
6
B
B address
SRL
CLK WE
DI1
A
O6
MC31
6
A
A address
SRL
CLK WE
DI1
A
O6
DMUX
MC31