Xilinx virtex-5 fpga

262 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
Table 6-20 lists the HSTL Class IV DC voltage specifications.
HSTL_II_T_DCI (1.5V) Split-Thevenin Termination
Figure 6-52 shows a sample circuit illustrating a valid termination technique for
HSTL_II_T_DCI (1.5V) with on-chip split-Thevenin termination. In this bidirectional case,
when 3-stated, the termination is invoked on the receiver and not on the driver.
Table 6-20: HSTL Class IV DC Voltage Specifications
Min Typ Max
V
CCO
1.40 1.50 1.60
V
REF
(2)
–0.90–
V
TT
– V
CCO
–
V
IH
V
REF
+0.1 – –
V
IL
––V
REF
–0.1
V
OH
V
CCO
–0.4 – –
V
OL
– – 0.4
I
OH
at V
OH
(mA)
(1)
–8 – –
I
OL
at V
OL
(mA)
(1)
48 – –
Notes:
1. V
OL
and V
OH
for lower drive currents are sample tested.
2. Per EIA/JESD8-6, “The value of V
REF
is to be selected by the user to provide optimum noise margin in
the use conditions specified by the user.”
X-Ref Target - Figure 6-52
Figure 6-52: HSTL_II_T_DCI (1.5V) Split-Thevenin Termination
ug190_6_90_041206
Z
0
IOB
IOB
HSTL_II_T_DCI
HSTL_II_T_DCI
V
CCO
= 1.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
REF
= 0.75V
+
–
DCI
V
REF
= 0.75V
Not 3-stated 3-stated