Xilinx virtex-5 fpga - Page 261

Virtex-5 FPGA User Guide www.xilinx.com 261
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
Figure 6-51 shows a sample circuit illustrating a valid bidirectional termination technique
for HSTL Class IV.
X-Ref Target - Figure 6-51
Figure 6-51: HSTL Class IV Bidirectional Termination
Z
0
IOB
IOB
HSTL_IV
HSTL_IV
ug190_6_49_030306
V
TT
= 1.5V
R
P
= Z
0
= 50Ω
V
TT
= 1.5V
R
P
= Z
0
= 50Ω
Z
0
IOB
IOB
HSTL_IV_DCI
HSTL_IV_DCI
V
CCO
= 1.5V
R
VRP
= Z
0
= 50Ω
V
REF
= 0.9V
V
REF
= 0.9V
+
–
V
REF
= 0.9V
+
–
External Termination
DCI
V
CCO
= 1.5V
R
VRP
= Z
0
= 50Ω
V
REF
= 0.9V