Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 147
UG190 (v5.0) June 19, 2009
FIFO Attributes
FIFO Attributes
Table 4-17 lists the FIFO18 and FIFO36 attributes. The size of the multirate FIFO can be
configured by setting the DATA_WIDTH attribute. The “FIFO VHDL and Verilog
Templates” section has examples for setting the attributes.
Table 4-17: FIFO18 and FIFO36 Attributes
Attribute Name Type Values Default Notes
ALMOST_FULL_OFFSET 13-bit
HEX
See Table 4-19 Setting determines the difference
between FULL and ALMOSTFULL
conditions. Must be set using
hexadecimal notation.
ALMOST_EMPTY_OFFSET 13-bit
HEX
See Table 4-19 Setting determines the difference
between EMPTY and ALMOSTEMPTY
conditions. Must be set using
hexadecimal notation.
FIRST_WORD_FALL_THROUGH Boolean FALSE,
TRUE
FALSE If TRUE, the first word written into the
empty FIFO appears at the FIFO output
without RDEN asserted.
DO_REG 1-bit
Binary
0, 1 1 For multirate (asynchronous) FIFO, must
be set to 1.
For synchronous FIFO, DO_REG must be
set to 0 for flags and data to follow a
standard synchronous FIFO operation.
When DO_REG is set to 1, effectively a
pipeline register is added to the output of
the synchronous FIFO. Data then has a
one clock cycle latency. However, the
clock-to-out timing is improved.
DATA_WIDTH Integer 4, 9, 18, 36, 72 4
LOC
(1, 2)
String Valid FIFO18 or
FIFO36 location
Sets the location of the FIFO18 or FIFO36.
EN_SYN Boolean FALSE,
TRUE
FALSE When set to TRUE, ties WRCLK and
RDCLK together.
When set to TRUE, FWFT must be
FALSE.
When set to FALSE, DO_REG must be 1.
Notes:
1. If FIFO18 is constrained to FIFO18_X#Y#, then RAMB18 can not be constrained to RAMB18_X#Y# since the same location would be
used.
2. If a FIFO18 is constrained to FIFO18_X#Y#, corresponding to the lower RAMB18_X#Y# of the RAMB18 pair, a RAMB18 can be
constrained to the upper RAMB18_X#Y# of the pair.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English