Xilinx virtex-5 fpga

42 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 1: Clock Resources
Regional Clock Buffer - BUFR
The regional clock buffer (BUFR) is another clock buffer available in Virtex-5 devices.
BUFRs drive clock signals to a dedicated clock net within a clock region, independent from
X-Ref Target - Figure 1-19
Figure 1-19: BUFIO Driving I/O Logic In a Single Clock Region
I/O
I/O
I/O
I/O
I/O
I/O
I/O
BUFIO
BUFIO
BUFR
BUFR
ug190_1_19_060706
To Fabric
To Adjacent
Region
To Adjacent
Region
I/O
I/O
I/O
Clock Capable I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
N
P
N
P
N
P
N
Not all available BUFIOs are shown.
Clock Capable I/O
Clock Capable I/O
Clock Capable I/O