Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 73
UG190 (v5.0) June 19, 2009
Connecting DCMs to Other Clock Resources in Virtex-5 Devices
Dynamic Reconfiguration
The Dynamic Reconfiguration Ports (DRPs) can update the initial DCM settings without
reloading a new bit stream to the FPGA. The DRP address mapping changed in Virtex-5
FPGAs. The Virtex-5 FPGA Configuration Guide provides more information on using DRPs.
Specific to the DCM, DRPs allow dynamic adjustment of the CLKFX_MULTIPLY(M) and
CLKFX_DIVIDE(D) values to produce a new CLKFX frequency.
The following steps are required when using DRPs to load new M and D values:
• Subtract the desired M and D values by one. For example, if the desired M/D = 9/4,
then load M/D = 8/3.
• Hold DCM in reset (assert RST signal) and release it after the new M and D values are
written. The CLKFX outputs can be used after LOCKED is asserted High again.
• Read DADDR0 to restore the default status on D0.
• Release RST.
Connecting DCMs to Other Clock Resources in Virtex-5 Devices
Most DCM functions require connection to dedicated clock resources, including dedicated
clock I/O (IBUFG), clock buffers (BUFGCTRLs), and PLLs. These clock resources are
located in the center column of the Virtex-5 devices. This section provides guidelines on
connecting the DCM to dedicated clock resources.
IBUFG to DCM
Virtex-5 devices contain 20 clock inputs. These clock inputs are accessible by instantiating
the IBUFG. Each top and bottom half of a Virtex-5 device contains 10 IBUFGs. Any of the
IBUFG in top or bottom half of the Virtex-5 device can drive the clock input pins (CLKIN,
CLKFB, PSCLK, or DCLK) of a DCM located in the same top/bottom half of the device.
DCM to BUFGCTRL
Any DCM clock output can drive any BUFGCTRL input in the same top/bottom half of
the device. There are no restrictions on how many DCM outputs can be used
simultaneously.
BUFGCTRL to DCM
Any BUFGCTRL can drive any DCM in the Virtex-5 devices. However, only up to ten
dedicated clock routing resources exist in a particular clock region. Since the clock routing
is accessed via the BUFGCTRL outputs, this indirectly limits the BUFGCTRL to DCM
connection. If ten BUFGCTRL outputs are already accessing a clock region, and a DCM is
in that region, then no additional BUFGCTRL can be used in that region, including a
connection to the CLKFB pin of the DCM.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English