Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 315
UG190 (v5.0) June 19, 2009
Simultaneous Switching Output Limits
Full Device SSO Calculator
A Microsoft Excel-based spreadsheet, the Virtex-5 FPGA SSO Calculator, automates all the
PFDM and SSO calculations. The Virtex-5 FPGA SSO calculator uses PCB geometry, (board
thickness, via diameter, and breakout trace width and length) to determine power system
inductance. It determines the smallest undershoot and logic-low threshold voltage among
all input devices, calculates the average output capacitance, and determines the SSO
allowance by taking into account all of the board-level design parameters mentioned in
this document. In addition, the Virtex-5 FPGA SSO calculator checks the adjacent bank and
package SSO ensuring the full device design does not exceed the SSO allowance. Since
bank-number assignment for Virtex-5 devices is different from package to package due to
its columnar architecture (versus the peripheral I/O architecture of previous devices),
there is a separate tab at the bottom of the SSO calculator display for each Virtex-5 FPGA
package. This customizing allows for the arrangement of physically adjacent banks (as
they appear clockwise on each unique package, even though they are not labeled in a
contiguous manner), and the hard-coding of the number of V
CCO
/GND pairs per bank.
The Virtex-5 FPGA SSO Calculator file (ug190_SSO_Calculator.zip) is available at:
https://secure.xilinx.com/webreg/clickthrough.do?cid=30154
.
Other SSO Assumptions
LVDCI and HSLVDCI Drivers
All limits for controlled impedance DCI I/O standards assume a 50 Ω output impedance.
For higher reference resistor (RR) values, less drive strength is needed, and the SSO limit
increases linearly. To calculate the SSO limit for a controlled impedance driver with
different reference resistors, the following formula is used:
Example
The designer uses LVDCI_18 driver with 65 Ω reference resistors. The LVDCI_18 SSO limit
for 50 Ω impedance is first taken from Table 6-40. The SSO limit for LVDCI_18 at 50 Ω is 11
SSO per V
CCO
/GND pin pair. Therefore, the SSO limit for LVDCI_18 at 65 Ω is:
SSO Limit LVDCI_18 at 65 Ω = ((65 Ω)/50 Ω) × 11 = 14.3
Bank 0
Bank 0 in all devices contains only configuration and dedicated signals. Since there is no
user I/O in Bank 0, no SSO analysis is necessary for this bank.
User SSO
User RR
50Ω
------------------------
Ω
⎝⎠
⎛⎞
SSO Limit for Ω()=

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English