Xilinx virtex-5 fpga User Manual

298 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different input, output, and bidirectional
standards in the same bank:
1. Combining output standards only. Output standards with the same output V
CCO
requirement can be combined in the same bank.
Compatible example:
SSTL2_I and LVDCI_25 outputs
Incompatible example:
SSTL2_I (output V
CCO
= 2.5V) and
LVCMOS33 (output V
CCO
= 3.3V) outputs
2. Combining input standards only. Input standards with the same V
CCO
and V
REF
requirements can be combined in the same bank.
Compatible example:
LVCMOS15 and HSTL_IV inputs
Incompatible example:
LVCMOS15 (input V
CCO
= 1.5V) and
LVCMOS18 (input V
CCO
= 1.8V) inputs
Incompatible example:
HSTL_I_DCI_18 (V
REF
= 0.9V) and
HSTL_IV_DCI_18 (V
REF
= 1.1V) inputs
3. Combining input standards and output standards. Input standards and output
standards with the same V
CCO
requirement can be combined in the same bank.
Compatible example:
LVDS_25 output and HSTL_I input
Incompatible example:
LVDS_25 output (output V
CCO
= 2.5V) and
HSTL_I_DCI_18 input (input V
CCO
= 1.8V)
4. Combining bidirectional standards with input or output standards. When
combining bidirectional I/O with other standards, make sure the bidirectional
standard can meet the first three rules.
5. Additional rules for combining DCI I/O standards.
a. No more than one Single Termination type (input or output) is allowed in the same
bank.
Incompatible example:
HSTL_IV_DCI input and HSTL_III_DCI input
b. No more than one Split Termination type (input or output) is allowed in the same
bank.
Incompatible example:
HSTL_I_DCI input and HSTL_II_DCI input
The implementation tools enforce these design rules.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English