Xilinx virtex-5 fpga User Manual

144 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 4: Block RAM
FIFO Operations
Reset
Reset is an asynchronous signal for both multirate and synchronous FIFO. Reset must be
asserted for three cycles to reset all read and write address counters and initialize flags
after power up. Reset does not clear the memory, nor does it clear the output register.
When reset is asserted High, EMPTY and ALMOST_EMPTY will be set to 1, FULL and
ALMOST_FULL will be reset to 0. The reset signal must be High for at least three read
clock and write clock cycles to ensure all internal states are reset to the correct values.
During RESET, RDEN and WREN must be held Low.
Operating Mode
There are two operating modes in FIFO functions. They differ only in output behavior
immediately after the first word is written to a previously empty FIFO.
Standard Mode
After the first word is written into an empty FIFO, the Empty flag deasserts synchronously
with RDCLK. After Empty is deasserted Low and RDEN is asserted, the first word will
appear at DO on the rising edge of RDCLK.
First Word Fall Through (FWFT) Mode
After the first word is written into an empty FIFO, this word automatically appears at DO
before RDEN is asserted. Subsequent Read operations require Empty to be Low and RDEN
to be High. Figure 4-20 illustrates the difference between standard mode and FWFT mode.
ALMOSTEMPTY Output Almost all valid entries in FIFO have been read.
Synchronous with RDCLK. The offset for this flag is user
configurable. See Table 4-16 for the clock latency for flag
deassertion.
RDCOUNT Output The FIFO data read pointer. It is synchronous with RDCLK.
The value will wrap around if the maximum read pointer
value has been reached.
WRCOUNT Output The FIFO data write pointer. It is synchronous with WRCLK.
The value will wrap around if the maximum write pointer
value has been reached.
WRERR Output When the FIFO is full, any additional write operation
generates an error flag. Synchronous with WRCLK.
RDERR Output When the FIFO is empty, any additional read operation
generates an error flag. Synchronous with RDCLK.
Table 4-15: FIFO I/O Port Names and Descriptions (Continued)
Port Name Direction Description

Xilinx virtex-5 fpga Specifications

General

Family	Virtex-5
Manufacturer	Xilinx
Category	FPGA
Technology	65nm
Maximum I/O Pins	Up to 1200
Power Consumption	Varies by model and configuration
Operating Temperature	Commercial, Industrial
Package Options	LXT, SXT, TXT
Clock Management Tiles	Up to 12
Transceivers	Up to 24 (depending on sub-family)

Summary

Chapter 1: Clock Resources

Global Clocking Resources

Details the dedicated network of interconnect for reaching clock inputs across the FPGA.

Global Clock Buffers

Describes the 32 global clock buffers and their role in accessing global clock trees and nets.

Clock Regions

Explains how devices are divided into regions for improved clock distribution and support for multiple clock domains.

Regional Clocking Resources

Covers clock networks independent of global network, useful for source-synchronous interfaces.

BUFR Primitive

Details the regional clock buffer primitive used for dividing input clock frequency.

Chapter 2: Clock Management Technology

DCM Summary

Overview of Digital Clock Managers (DCMs) and their powerful clock management features.

DCM Primitives

Introduces the basic DCM primitives: DCM_BASE and DCM_ADV.

DCM Ports

Details the four types of DCM ports: Clock Input, Control/Data Input, Clock Output, and Status/Data Output.

DCM Attributes

Describes various attributes that govern DCM functionality and their application.

DCM Design Guidelines

Provides detailed descriptions and guidelines for using Virtex-5 FPGA DCMs.

Chapter 3: Phase-Locked Loops (PLLs)

PLL Primitives

Introduces the two Virtex-5 FPGA PLL primitives: PLL_BASE and PLL_ADV.

PLL_ADV Primitive

Details features and ports of the PLL_ADV primitive, including clock switching.

Clock Network Deskew

Explains how PLLs or DLLs compensate for clock network delay.

Frequency Synthesis Only

Discusses using PLLs for standalone frequency synthesis.

PLL Programming

Outlines the flow for programming PLLs to guarantee stability and performance.

Chapter 4: Block RAM

Block RAM Introduction

Describes the large number of 36 Kb block RAMs in Virtex-5 devices and their features.

Synchronous Dual-Port and Single-Port RAMs

Details the structure and data flow of true dual-port block RAM memories.

Write Modes

Explains the behavior of data available on output latches after a write clock edge.

Block RAM Error Correction Code

Covers the 64-bit ECC implementation for detecting and correcting single/double-bit errors.

Block RAM Port Signals

Details the signals for each block RAM port, including clock, enable, and address buses.

Chapter 5: Configurable Logic Blocks (CLBs)

Slice Description

Describes the components within a slice: logic-function generators, storage elements, and multiplexers.

Look-Up Table (LUT)

Explains the implementation of function generators as six-input look-up tables (LUTs).

Storage Elements

Details the configuration of storage elements as D-type flip-flops or level-sensitive latches.

Distributed RAM and Memory (Available in SLICEM only)

Covers how multiple LUTs in SLICEMs can implement synchronous RAM resources.

CLB / Slice Timing Models

Explains timing parameters and diagrams for CLBs and slices.

Chapter 6: SelectIO Resources

SelectIO Resources Introduction

Overviews configurable high-performance SelectIO drivers and receivers supporting various interfaces.

SelectIO Resources General Guidelines

Summarizes general guidelines for designing with SelectIO resources in Virtex-5 FPGAs.

Virtex-5 FPGA Digitally Controlled Impedance (DCI)

Explains DCI technology for adjusting I/O impedance to match transmission lines.

Rules for Combining I/O Standards in the Same Bank

Details the rules for combining different input, output, and bidirectional standards within the same I/O bank.

Chapter 7: SelectIO Logic Resources

Input Serial-to-Parallel Logic Resources (ISERDES)

Describes dedicated serial-to-parallel converters supporting high-speed source-synchronous applications.

IDDR Overview

Explains the dedicated registers in ILOGIC for implementing input Double-Data-Rate (DDR) registers.

Input/Output Delay Element (IODELAY)

Details the programmable absolute delay element for I/O blocks.

IDELAYCTRL Overview

Explains the module that calibrates delay elements for process, voltage, and temperature variations.

OLOGIC Resources

Covers resources for configuring output data path and 3-state control path.

Chapter 8: Advanced SelectIO Logic Resources

Input Serial-to-Parallel Logic Resources (ISERDES)

Describes dedicated serial-to-parallel converters supporting high-speed source-synchronous applications.

ISERDES_NODELAY Attributes

Details attributes for the ISERDES_NODELAY primitive.

Output Parallel-to-Serial Logic Resources (OSERDES)

Describes dedicated parallel-to-serial converters for high-speed source-synchronous interfaces.

OSERDES Attributes

Details attributes available for the OSERDES primitive.