Xilinx virtex-5 fpga - Differential HSTL Class I

Virtex-5 FPGA User Guide www.xilinx.com 253
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
Differential HSTL Class I
Figure 6-41 shows a sample circuit illustrating a valid termination technique for
differential HSTL Class I (1.5V) with unidirectional termination.
Figure 6-42 shows a sample circuit illustrating a valid termination technique for
differential HSTL Class I (1.5V) with unidirectional DCI termination.
X-Ref Target - Figure 6-41
Figure 6-41: Differential HSTL (1.5V) Class I Unidirectional Termination
X-Ref Target - Figure 6-42
Figure 6-42: Differential HSTL (1.5V) Class I DCI Unidirectional Termination
ug190_6_39_030206
+
–
External Termination
Z
0
IOB
IOB
DIFF_HSTL_I
DIFF_HSTL_I
Z
0
DIFF_HSTL_I
V
TT
= 0.75V
50Ω
V
TT
= 0.75V
50Ω
ug190_6_40_030206
IOB
DIFF_HSTL_I_DCI
DIFF_HSTL_I_DCI
V
CCO
= 1.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
+
–
DCI
DIFF_HSTL_I_DCI
V
CCO
= 1.5V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
IOB
Z
0
Z
0