Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 215
UG190 (v5.0) June 19, 2009
CLB Primitives
Multiplexer Primitives
Two primitives (MUXF7 and MUXF8) are available for access to the dedicated F7AMUX,
F7BMUX and F8MUX in each slice. Combined with LUTs, these multiplexer primitives are
also used to build larger width multiplexers (from 8:1 to 16:1). The “Designing Large
Multiplexers” section provides more information on building larger multiplexers.
Port Signals
Data In – I0, I1
The data input provides the data to be selected by the select signal (S).
Control In – S
The select input signal determines the data input signal to be connected to the output O.
Logic 0 selects the I0 input, while logic 1 selects the I1 input.
Data Out – O
The data output O provides the data value (one bit) selected by the control inputs.
Carry Chain Primitive
The CARRY4 primitive represents the fast carry logic for a slice in the Virtex-5 architecture.
This primitive works in conjunction with LUTs in order to build adders and multipliers.
This primitive is generally inferred by synthesis tools from standard RTL code. The
synthesis tool can identify the arithmetic and/or logic functionality that best maps to this
X-Ref Target - Figure 5-35
Figure 5-35: Example Static-Length Shift Register
LUT
SRLC32G
D
Q31
LUT
SRLC32G
D
Q31
LUT
SRLC32G
D OUT
(72-bit SRL)
A[4:0]
Q31
Q
5
00111
D
UG190_5_35_050506
LUT
SRLC32G
D
Q31
LUT
SRLC32G
D
Q31
LUT
SRLC32G
D OUT
(72-bit SRL)
A[4:0]
Q31
Q
FF
D
Q
5
00110
D

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English