Xilinx virtex-5 fpga

216 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 5: Configurable Logic Blocks (CLBs)
logic in terms of performance and area. It also automatically uses and connects this
function properly. Figure 5-24, page 199 illustrates the CARRY4 block diagram.
Port Signals
Sum Outputs – O[3:0]
The sum outputs provide the final result of the addition/subtraction.
Carry Outputs – CO[3:0]
The carry outputs provide the carry out for each bit. A longer carry chain can be created if
CO[3] is connected to CI input of another CARRY4 primitive.
Data Inputs – DI[3:0]
The data inputs are used as “generate” signals to the carry lookahead logic. The “generate”
signals are sourced from LUT outputs.
Select Inputs – S[3:0]
The select inputs are used as “propagate” signals to the carry lookahead logic. The
“propagate” signals are sourced from LUT outputs.
Carry Initialize – CYINIT
The carry initialize input is used to select the first bit in a carry chain. The value for this pin
is either 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry bit).
Carry In – CI
The carry in input is used to cascade slices to form longer carry chain. To create a longer
carry chain, the CO[3] output of another CARRY4 is simply connected to this pin.