Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 359
UG190 (v5.0) June 19, 2009
Input Serial-to-Parallel Logic Resources (ISERDES)
DATA_WIDTH Attribute
The DATA_WIDTH attribute defines the parallel data output width of the serial-to-parallel
converter. The possible values for this attribute depend on the INTERFACE_TYPE and
DATA_RATE attributes. See Table 8-3 for recommended data widths.
When the DATA_WIDTH is set to widths larger than six, a pair of ISERDES_NODELAY
must be configured into a master-slave configuration. See “ISERDES Width Expansion.”
Width expansion is not allowed in memory mode.
INTERFACE_TYPE Attribute
The INTERFACE_TYPE attribute determines whether the ISERDES_NODELAY is
configured in memory or networking mode. The allowed values for this attribute are
MEMORY or NETWORKING. The default mode is MEMORY.
When INTERFACE_TYPE is set to NETWORKING, the Bitslip submodule is available and
the OCLK port is unused. BITSLIP_ENABLE must be set to TRUE, and the Bitslip port tied
Low to disable Bitslip operation when the Bitslip module is not used in networking mode.
When set to MEMORY, the Bitslip submodule is not available (BITSLIP_ENABLE must be
set to FALSE), and the OCLK port can be used.
Figure 8-5 illustrates the ISERDES_NODELAY internal connections when in Memory
mode.
Table 8-3: Recommended Data Widths
INTERFACE_TYPE DATA_RATE Recommended Data Widths
NETWORKING
SDR 2, 3, 4, 5, 6, 7, 8
DDR 4, 6, 8, 10
MEMORY
SDR None
DDR 4

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English