Xilinx virtex-5 fpga - Differential SSTL Class II (1.8 V)

Virtex-5 FPGA User Guide www.xilinx.com 291
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
Differential SSTL Class II (1.8V)
Figure 6-82 shows a sample circuit illustrating a valid termination technique for
differential SSTL Class II (1.8V) with unidirectional termination.
Figure 6-83 shows a sample circuit illustrating a valid termination technique for
differential SSTL Class II (1.8V) with unidirectional DCI termination.
X-Ref Target - Figure 6-82
Figure 6-82: Differential SSTL (1.8V) Class II Unidirectional Termination
ug190_6_77_030506
+
–
External Termination
Z
0
IOB
IOB
DIFF_SSTL18_II
DIFF_SSTL18_II
Z
0
DIFF_SSTL18_II
V
TT
= 0.9V
50Ω
50Ω
V
TT
= 0.9V
V
TT
= 0.9V
50Ω
50Ω
V
TT
= 0.9V
R
S
= 20Ω
R
S
= 20Ω
X-Ref Target - Figure 6-83
Figure 6-83: Differential SSTL (1.8V) Class II Unidirectional DCI Termination
ug190_6_78_030506
IOB
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
+
–
DCI
DIFF_SSTL18_II_DCI
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
IOB
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
CCO
= 1.8V
Z
0
Z
0
R
0
= 20Ω
R
0
= 20Ω