Xilinx virtex-5 fpga

292 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
Figure 6-84 shows a sample circuit illustrating a valid termination technique for
differential SSTL Class II (1.8V) with bidirectional termination.
Figure 6-85 shows a sample circuit illustrating a valid termination technique for
differential SSTL Class II (1.8V) with bidirectional DCI termination.
X-Ref Target - Figure 6-84
Figure 6-84: Differential SSTL (1.8V) Class II with Bidirectional Termination
Z
0
IOB
IOB
DIFF_SSTL18_II DIFF_SSTL18_II
+
–
External Termination
V
TT
= 0.9V
50Ω
V
TT
= 0.9V
50Ω
DIFF_SSTL18_II
ug190_6_79_091807
Z
0
DIFF_SSTL18_II
DIFF_SSTL18_II DIFF_SSTL18_II
+
–
V
TT
= 0.9V
50Ω
V
TT
= 0.9V
50Ω
20Ω
20Ω
20Ω
20Ω
X-Ref Target - Figure 6-85
Figure 6-85: Differential SSTL (1.8V) Class II with DCI Bidirectional Termination
Z
0
IOB
IOB
DIFF_SSTL18_II_DCI DIFF_SSTL18_II_DCI
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
+
–
DCI
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
DIFF_SSTL18_II_DCI
ug190_6_80_030506
Z
0
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI DIFF_SSTL18_II_DCI
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
+
–
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
R
0
= 20Ω
R
0
= 20Ω
R
0
= 20Ω
R
0
= 20Ω