Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 151
UG190 (v5.0) June 19, 2009
FIFO Timing Models and Parameters
Case 1: Writing to an Empty FIFO
Prior to the operations performed in Figure 4-21, the FIFO is completely empty.
Clock Event 1 and Clock Event 3: Write Operation and Deassertion of EMPTY
Signal
During a write operation to an empty FIFO, the content of the FIFO at the first address is
replaced by the data value on the DI pins. Three read-clock cycles later (four read-clock
cycles for FWFT mode), the EMPTY pin is deasserted when the FIFO is no longer empty.
The RDCOUNT also increments by one due to an internal read preloading the data to the
output registers.
For the example in Figure 4-21, the timing diagram is drawn to reflect FWFT mode. Clock
event 1 is with respect to the write-clock, while clock event 3 is with respect to the read-
clock. Clock event 3 appears four read-clock cycles after clock event 1.
• At time T
FDCK_DI
, before clock event 1 (WRCLK), data 00 becomes valid at the DI
inputs of the FIFO.
• At time T
FCCK_WREN
, before clock event 1 (WRCLK), write enable becomes valid at
the WREN input of the FIFO.
• At time T
FCKO_DO
, after clock event 3 (RDCLK), data 00 becomes valid at the DO
output pins of the FIFO. In standard mode, data 00 does not appear at the DO output
pins of the FIFO.
• At time T
FCKO_EMPTY
, after clock event 3 (RDCLK), EMPTY is deasserted. In standard
mode, EMPTY is deasserted one read-clock earlier than clock event 3.
If the rising WRCLK edge is close to the rising RDCLK edge, EMPTY could be deasserted
one RDCLK period later.
X-Ref Target - Figure 4-21
Figure 4-21: Writing to an Empty FIFO in FWFT Mode
ug190_4_18_032506
00
1423
01 02 03 04
00
05 06
WRCLK
WREN
DI
RDCLK
RDEN
DO
EMPTY
AEMPTY
T
FCCK_WREN
T
FDCK_DI
T
FDCK_DI
T
FCKO_DO
T
FCKO_EMPTY
T
FCKO_AEMPTY

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English