Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 305
UG190 (v5.0) June 19, 2009
Simultaneous Switching Output Limits
Simultaneous Switching Output Limits
When multiple output drivers change state at the same time, power supply disturbance
occurs. These disturbances can cause undesired transient behavior in output drivers, input
receivers, or in internal logic. These disturbances are often referred to as Simultaneous-
Switching Output (SSO) noise. The SSO limits govern the number and type of I/O output
drivers that can be switched simultaneously while maintaining a safe level of SSO noise.
Sparse-Chevron Packages
Virtex-5 FPGA packaging utilizes a sparse-chevron pinout arrangement. The sparse-
chevron pinout style is an improvement over previous designs, offering low crosstalk and
SSO noise. The pinout is designed to minimize PDS inductance and keep I/O signal return
current paths very closely coupled to their associated I/O signal.
The maximum ratio of I/O to reference pins (V
CCO
and GND) in sparse-chevron packages
is 4:1. For every four I/O pins, there is always at least one reference pin.
For boards that do not meet the nominal PCB requirements listed in “Nominal PCB
Specifications,” the Virtex-5 FPGA SSO calculator is available, containing all SSO limit data
for all I/O standards. For designs in nominal PCBs mixing limited and “no limit” I/O
standards, the Virtex-5 FPGA SSO calculator must be used to ensure that I/O utilization
does not exceed the limit. Information on the calculator is available under the “Full Device
SSO Calculator” section.
Unlike devices in previous families, Virtex-5 devices have only two bank sizes: 20 I/O and
40 I/O. With the ratio of signal to reference pins always constant, the SSO capacity of all
banks of 20 I/O are the same, and the capacity of all banks of 40 I/O are the same. The SSO
limits for Virtex-5 devices are listed on a per-bank basis rather than a limit per V
CCO
/GND
pair.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English