Xilinx virtex-5 fpga User Manual

320 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 7: SelectIO Logic Resources
SAME_EDGE Mode
In the SAME_EDGE mode, the data is presented into the FPGA fabric on the same clock
edge. However, the data pair to be separated by one clock cycle. This structure is similar to
the Virtex-II, Virtex-II Pro, and Virtex-4 FPGA implementation.
Figure 7-3 shows the timing diagram of the input DDR using SAME_EDGE mode. In the
timing diagram, the output pairs Q1 and Q2 are no longer (0) and (1). Instead, the first pair
presented is pair Q1 and Q2 (0) and (don't care) respectively, followed by pair (1) and (2) on
the next clock cycle.
SAME_EDGE_PIPELINED Mode
In the SAME_EDGE_PIPELINED mode, the data is presented into the FPGA fabric on the
same clock edge.
Unlike the SAME_EDGE mode, the data pair is not separated by one clock cycle. However,
an additional clock latency is required to remove the separated effect of the SAME_EDGE
mode. Figure 7-4 shows the timing diagram of the input DDR using the
SAME_EDGE_PIPELINED mode. The output pairs Q1 and Q2 are presented to the FPGA
fabric at the same time.
X-Ref Target - Figure 7-2
Figure 7-2: Input DDR Timing in OPPOSITE_EDGE Mode
ug190_7_02_041206
C
CE
D
Q1
Q2
D0A D1A D2A
D0A D2A D4A D6A D8A D10A D12A
D1A D3A D5A D7A D9A D11A
D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A
X-Ref Target - Figure 7-3
Figure 7-3: Input DDR Timing in SAME_EDGE Mode
ug190_7_03_041206
C
CE
D
Q1
Q2
D1A
D0A D2A D4A D6A D8A D10A
D1A D3A D5A D7A D9A D11A
D3A D5A D7A D9A D11A
D0A D2A D4A D6A D8A D10A
Don't care

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English