Xilinx virtex-5 fpga User Manual

366 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 8: Advanced SelectIO Logic Resources
BITSLIP Submodule
All ISERDES blocks in Virtex-5 devices contain a Bitslip submodule. This submodule is
used for word-alignment purposes in source-synchronous networking-type applications.
Bitslip reorders the parallel data in the ISERDES block, allowing every combination of a
repeating serial pattern received by the deserializer to be presented to the FPGA fabric.
This repeating serial pattern is typically called a training pattern (training patterns are
supported by many networking and telecom standards).
Bitslip Operation
By asserting the Bitslip pin of the ISERDES block, the incoming serial data stream is
reordered at the parallel side. This operation is repeated until the training pattern is seen.
The tables in Figure 8-10 illustrate the effects of a Bitslip operation in SDR and DDR mode.
For illustrative purposes the data width is eight. The Bitslip operation is synchronous to
CLKDIV. In SDR mode, every Bitslip operation causes the output pattern to shift left by
one. In DDR mode, every Bitslip operation causes the output pattern to alternate between
a shift right by one and shift left by three. In this example, on the eighth Bitslip operation,
the output pattern reverts to the initial pattern. This assumes that serial data is an eight bit
repeating pattern.
X-Ref Target - Figure 8-10
Figure 8-10: Bitslip Operation Examples
ug190_8_10_100307
Bitslip
Operations
Executed
Output
Pattern (8:1)
00100111
01001110
10011100
00111001
01110010
11100100
11001001
10010011
Initial
1
2
3
4
5
6
7
Bitslip Operation in SDR Mode
Bitslip
Operations
Executed
Output
Pattern (8:1)
10010011
10011100
01001110
01110010
00111001
11001001
11100100
00100111
Initial
1
2
3
4
5
6
7
Bitslip Operation in DDR Mode

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English