Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 367
UG190 (v5.0) June 19, 2009
Input Serial-to-Parallel Logic Resources (ISERDES)
Figure 8-11 illustrates the ISERDES configured in 1:8 SDR mode with Bitslip_ENABLE set
to TRUE. Two ISERDES modules are in a master-slave configuration for a data width of
eight.
Guidelines for Using the Bitslip Submodule
Set the BITSLIP_ENABLE attribute to TRUE. When BITSLIP_ENABLE is set to FALSE, the
Bitslip pin has no effect. In a master-slave configuration, the BITSLIP_ENABLE attribute in
both modules must be set to TRUE.
To invoke a Bitslip operation, the BITSLIP port must be asserted High for one CLKDIV
cycle. In SDR mode, Bitslip cannot be asserted for two consecutive CLKDIV cycles; Bitslip
must be deasserted for at least one CLKDIV cycle between two Bitslip assertions. In both
SDR and DDR mode, the total latency from when the ISERDES captures the asserted
Bitslip input to when the “bit-slipped” ISERDES outputs Q1–Q6 are sampled into the
FPGA logic by CLKDIV is two CLKDIV cycles.
X-Ref Target - Figure 8-11
Figure 8-11: Circuit Diagram for Bitslip Configuration in 1:8 SDR Mode
Initial
1st
Bitslip
2nd
Bitslip
3th
Bitslip
4th
Bitslip
5th
Bitslip
6th
Bitslip
7th
Bitslip
BITSLIP_ENABLE = TRUE
BITSLIP_ENABLE = TRUE
BITSLIP
BITSLIP
Bitslip signal from system
8th Bitslip
(Back to initial)
Q1D
1001 0011
Q2
(Q7)Q3
(Q8)Q4
ISERDES
(Slave)
SERDES_MODE=SLAVE
IOB
Q5
Q6
Q1D
Q2
Q3
Q4
ISERDES
(Master)
SERDES_MODE=MASTER
Q5
Q6
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
0
1
1
1
0
0
0
1
0
0
1
1
1
1
0
0
1
0
0
1
1
SHIFTOUT1 SHIFTOUT2
SHIFTIN1 SHIFTIN2
ug190_8_11_100307
(Repeating
Pattern)

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English