Xilinx virtex-5 fpga - SSTL18 Class I (1.8 V)

Virtex-5 FPGA User Guide www.xilinx.com 285
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
SSTL18 Class I (1.8V)
Figure 6-77 shows a sample circuit illustrating a valid termination technique for SSTL
Class I (1.8V).
X-Ref Target - Figure 6-77
Figure 6-77: SSTL18 (1.8V) Class I Termination
Z
0
IOB
SSTL18_I
R
S
= 20Ω
IOB
SSTL18_I_DCI
R
0
= 20Ω
Z
0
IOB
SSTL18_I
ug190_6_72_030506
V
TT
= 0.9V
50Ω
Z
0
IOB
SSTL18_I_DCI
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
REF
= 0.9V
+
–
V
REF
= 0.9V
+
–
External Termination
DCI