Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 171
UG190 (v5.0) June 19, 2009
Legal Block RAM and FIFO Combinations
Block RAM ECC VHDL and Verilog Templates
VHDL and Verilog templates are available in the Libraries Guide.
Legal Block RAM and FIFO Combinations
The block RAM–FIFO combinations shown in Figure 4-33 are supported in a single
RAMB36 primitive. When placing block RAM and FIFO primitives in the same location,
the FIFO must occupy the lower port.
X-Ref Target - Figure 4-33
Figure 4-33: Legal Block RAM and FIFO Combinations
ug0190_4_35_050208
RAMB18
RAMB18
RAMB18
FIFO18
RAMB18SDP
RAMB18SDP
RAMB18SDP
FIFO18_36

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English