Xilinx virtex-5 fpga - Differential HSTL Class II (1.8 V)

Virtex-5 FPGA User Guide www.xilinx.com 267
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
Table 6-23 lists the HSTL Class II (1.8V) DC voltage specifications.
Differential HSTL Class II (1.8V)
Figure 6-58 shows a sample circuit illustrating a valid termination technique for
differential HSTL Class II (1.8V) with unidirectional termination.
Table 6-23: HSTL Class II (1.8V) DC Voltage Specifications
Min Typ Max
V
CCO
1.7 1.8 1.9
V
REF
(2)
– 0.9 –
V
TT
– V
CCO
× 0.5 –
V
IH
V
REF
+0.1 – –
V
IL
––V
REF
–0.1
V
OH
V
CCO
–0.4 – –
V
OL
– – 0.4
I
OH
at V
OH
(mA)
(1)
–16 – –
I
OL
at V
OL
(mA)
(1)
16 – –
Notes:
1. V
OL
and V
OH
for lower drive currents are sample tested.
2. Per EIA/JESD8-6, “The value of V
REF
is to be selected by the user to provide optimum noise margin in
the use conditions specified by the user.”
X-Ref Target - Figure 6-58
Figure 6-58: Differential HSTL (1.8V) Class II Unidirectional Termination
ug190_6_55_030306
+
–
External Termination
Z
0
IOB
IOB
DIFF_HSTL_II_18
DIFF_HSTL_II_18
Z
0
DIFF_HSTL_II_18
V
TT
= 0.9V
50Ω
V
TT
= 0.9V
50Ω
V
TT
= 0.9V
50Ω
V
TT
= 0.9V
50Ω