Xilinx virtex-5 fpga User Manual

268 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
Figure 6-59 shows a sample circuit illustrating a valid termination technique for
differential HSTL Class II (1.8V) with unidirectional DCI termination.
Figure 6-60 shows a sample circuit illustrating a valid termination technique for
differential HSTL Class II (1.8V) with bidirectional termination.
X-Ref Target - Figure 6-59
Figure 6-59: Differential HSTL (1.8V) Class II DCI Unidirectional Termination
ug190_6_56_121506
IOB
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II_DCI_18
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
+
–
DCI
DIFF_HSTL_II_DCI_18
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
IOB
V
CCO
= 1.8V
2R
VRN
= 2Z
0
= 100Ω
2R
VRP
= 2Z
0
= 100Ω
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
V
CCO
= 1.8V
Z
0
Z
0
X-Ref Target - Figure 6-60
Figure 6-60: Differential HSTL (1.8V) Class II Bidirectional Termination
Z
0
IOB
IOB
DIFF_HSTL_II_18 DIFF_HSTL_II_18
+
–
External Termination
V
TT
= 0.9V
50Ω
DIFF_HSTL_II_18
ug190_6_57_030306
Z
0
DIFF_HSTL_II_18
DIFF_HSTL_II_18 DIFF_HSTL_II_18
+
–
V
TT
= 0.9V
50Ω
V
TT
= 0.9V
50Ω
V
TT
= 0.9V
50Ω

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English