Xilinx virtex-5 fpga User Manual

306 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
Nominal PCB Specifications
The nominal SSO table (Table 6-40) contains SSO limits for cases where the PCB
parameters meet the following requirements.
Note:
In cases where PCB parameters do not meet all requirements listed below, the Virtex-5 FPGA
SSO Calculator must be used to determine the SSO limit, according to the physical factors of the
unique PCB.
PCB Construction
• V
CCO
and GND vias should have a drill diameter no less than 11 mils (279 µ).
• Total board thickness must be no greater than 62 mils (1575 µ).
Signal Return Current Management
• Traces must be referenced to a plane on an adjacent PCB layer.
• The reference plane must be either GND or the V
CCO
associated with the output
driver.
• The reference layer must remain uninterrupted for its full length from device to
device.
Load Traces
• All IOB output buffers must drive controlled impedance traces with characteristic
impedance of 50Ω ± 10%.
• Total capacitive loading at the far end of the trace (input capacitance of receiving
device) must be no more than 10 pF.
Power Distribution System Design
• Designed according to the Virtex-5 FPGA PCB Designer’s Guide.
♦ Decoupling capacitors per the device guideline
♦ Approved solder land patterns
• V
CCO
and GND planes cannot be separated by more than 5.0 mils (152 µ)

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English