Xilinx virtex-5 fpga User Manual

382 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 8: Advanced SelectIO Logic Resources
Clock Event 2
The reset pulse is deasserted on the rising edge of CLKDIV. The difference in propagation
delay between the two OSERDES causes the SR input to come out of reset on two different
CLK cycles. Without internal retiming, OSERDES1 finishes reset one CLK cycle before
OSERDES0 and both OSERDES are asynchronous.
Clock Event 3
The release of the reset signal at the SR input is retimed internally to CLKDIV. This
synchronizes OSERDES0 and OSERDES1.
Clock Event 4
The release of the reset signal at the SR input is retimed internally to CLK.
OSERDES VHDL and Verilog Instantiation Templates
The Libraries Guide includes instantiation templates of the OSERDES module in VHDL
and Verilog.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English