Xilinx virtex-5 fpga User Manual

88 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 2: Clock Management Technology
Legacy Support
The Virtex-5 FPGA DCMs (DCM_BASE and DCM_ADV) have exactly the same port
names as the Virtex-4 FPGA DCMs. However, the DRP address mapping has changed.
Refer to the Virtex-5 FPGA Configuration Guide for more information.
The Virtex-5 device supports the Virtex-II family and Virtex-II Pro FPGA DCM primitives.
The mapping of Virtex-II or Virtex-II Pro FPGA DCMs to Virtex-5 FPGA DCM_ADVs are
as follows:
• CLKIN, CLKFB, PSCLK, PSINDEC, PSEN, RST, CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X180, CLKFX, CLKFX180, CLKDV, PSDONE, LOCKED of Virtex-5
FPGA primitives (DCM_BASE/DCM_ADV) map to the same corresponding pins of a
Virtex-II or Virtex-II Pro FPGA DCM.
• Dynamic reconfiguration pins of Virtex-5 FPGA DCM_ADV are not accessible when a
Virtex-II or Virtex-II Pro FPGA DCM is used, except for DO[15:0].
• DO[7:0] pins of Virtex-5 FPGA DCM_ADV map to Status[7:0] of the Virtex-II or
Virtex-II Pro FPGA DCMs. DO[15:8] of DCM_ADV are not available when using
Virtex-II or Virtex-II Pro FPGA DCMs.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English