Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 113
UG190 (v5.0) June 19, 2009
Chapter 4
Block RAM
Block RAM Summary
The block RAM in Virtex-5 FPGAs stores up to 36K bits of data and can be configured as
either two independent 18 Kb RAMs, or one 36 Kb RAM. Each 36 Kb block RAM can be
configured as a 64K x 1 (when cascaded with an adjacent 36 Kb block RAM), 32K x 1,
16K x 2, 8K x 4, 4K x 9, 2K x 18, or 1K x 36 memory. Each 18 Kb block RAM can be
configured as a 16K x 1, 8K x2 , 4K x 4, 2K x 9, or 1K x 18 memory.
Similar to the Virtex-4 FPGA block RAMs, Write and Read are synchronous operations; the
two ports are symmetrical and totally independent, sharing only the stored data. Each port
can be configured in one of the available widths, independent of the other port. In
addition, the read port width can be different from the write port width for each port. The
memory content can be initialized or cleared by the configuration bitstream. During a
write operation the memory can be set to have the data output either remain unchanged,
reflect the new data being written or the previous data now being overwritten.
Virtex-5 FPGA block RAM enhancements include:
• Increased memory storage capability per block. Each block RAM can store up to 36K
bits of data.
• Support of two independent 18K blocks, or a single 36K block RAM.
• Each 36K block RAM can be set to simple dual-port mode, doubling data width of the
block RAM to 72 bits. The 18K block RAM can also be set to simple dual-port mode,
doubling data width to 36 bits. Simple dual-port mode is defined as having one read-
only port and one write-only port with independent clocks.
• Two adjacent block RAMs can be combined to one deeper 64K x 1 memory without
any external logic.
• One 64-bit Error Correction Coding block is provided per 36 Kb block RAM or 36 Kb
FIFO. Separate encode/decode functionality is available.
• Synchronous Set/Reset of the outputs to an initial value is available for both the latch
and register modes of the block RAM output.
• An attribute to configure the block RAM as a synchronous FIFO to eliminate flag
latency uncertainty.
• The Virtex-5 FIFO does not have FULL flag assertion latency.
Virtex-5 FPGA block RAM features:
• 18, 36, or 72-bit wide ports can have an individual write enable per byte. This feature
is popular for interfacing to an on-chip microprocessor.
• Each block RAM contains optional address sequencing and control circuitry to
operate as a built-in multirate FIFO memory. In Virtex-5 architecture, the block RAM
can be configured as an 18Kb or 36Kb FIFO.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English