Xilinx virtex-5 fpga User Manual

374 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 8: Advanced SelectIO Logic Resources
OSERDES Attributes
Table 8-7 lists and describes the various attributes that are available for the OSERDES
primitive. The table includes the default values.
DATA_RATE_OQ Attribute
The DATA_RATE_OQ attribute defines whether data is processed as single data rate (SDR)
or double data rate (DDR). The allowed values for this attribute are SDR and DDR. The
default value is DDR.
DATA_RATE_TQ Attribute
The DATA_RATE_TQ attribute defines whether 3-state control is to be processed as single
data rate (SDR) or double data rate (DDR). The allowed values for this attribute are SDR
and DDR. The default value is DDR.
Table 8-7: OSERDES Attribute Summary
OSERDES Attribute Description Value Default Value
DATA_RATE_OQ Defines whether data (OQ) changes at every
clock edge or every positive clock edge with
respect to CLK.
String: SDR or DDR DDR
DATA_RATE_TQ Defines whether the 3-state (TQ) changes at
every clock edge, every positive clock edge
with respect to clock, or is set to buffer
configuration.
String: BUF, SDR, or DDR DDR
DATA_WIDTH Defines the parallel-to-serial data converter
width. This value also depends on the
DATA_RATE_OQ value.
Integer: 2, 3, 4, 5, 6, 7, 8, or 10.
If DATA_RATE_OQ = DDR,
value is limited to 4, 6, 8, or 10.
If DATA_RATE_OQ = SDR,
value is limited to
2, 3, 4, 5, 6, 7, or 8.
4
SERDES_MODE Defines whether the OSERDES module is a
master or slave when using width expansion.
String: MASTER or SLAVE MASTER
TRISTATE_WIDTH Defines the parallel to serial 3-state converter
width.
Integer: 1 or 4
If DATA_RATE_TQ = DDR,
DATA_WIDTH = 4, and
DATA_RATE_OQ = DDR,
value is limited to 4.
For all other settings of
DATA_RATE_TQ,
DATA_WIDTH, and
DATA_RATE_OQ, value is
limited to 1.
4

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English